The invention generally relates to frequency locked loop circuits, and, more particularly, to a frequency locked loop utilizing binary rate multipliers for improved stability.
In the design of so called Phase Locked Loops (PLL""s) it is the intention of the designer to create an output frequency that is related in some why to a known reference frequency. PLLs are often used to control the frequency of phase of a signal, or both. The relationship is commonly Fout=(M/N)*Fref. Where Fref is the input reference frequency of an input signal, and Fout is the resulting output signal. The factors of M and N are generated by conventional analytical circuit components to divide an input signal. This gives an output signal of a different frequency than the input signal. Generally, most conventional PLL implementations proceed as follows. Since
Fout=(M/N) Fref, it follows that Fout/M=Fref/N. Hence digital dividers are provided to create the common frequency Fout/M, which is the same as Fref/N, and a means referred to as a Frequency detector is employed. The frequency detector is operable at this common frequency and configured with analog filter components to control a Voltage Controlled Oscillator (VCO) that is responsible for generating the desired output frequency, Fout. By use of feedback it can be shown that the VCO may be made to xe2x80x9clockxe2x80x9d onto the correct frequency and further adjustment within the loop then ceases when Fout/M is indeed equal to Fref/N. This clearly then is a feedback loop, where the difference between Fout/M and Fref/N, the output from the frequency detector, is the error signal driving the loop.
One common problem exists that loop is of order greater than one because a phase difference is detected in the frequency detector. This is because phase, being the integral of frequency, implies that there is a 90 degree phase shifted response from the VCO input voltage. This is mathematically to imply that there is a pole in the loop response created by the action of measuring phase in the frequency detector and controlling frequency in the VCO. Thus, the analog filter is complex and is required to have a zero to remove the inherent pole. Thus it is at least a second order control system requiring two frequency dependant devices (commonly two capacitors) of known and predictable ratio.
Secondly, the signal to adjust the loop is derived from the frequency detector. As a result, the error signal is available at the rate of Fout/M in most cases. For the cases when M and N are factors that cannot be further reduced, such as prime factors, the frequency detectors are unable to reduce a large fraction of M/N to a manageable number. For example, a fraction of {fraction (1771/3997)}, two prime factors that cannot be further reduced, would yield the fractions of the input frequency divided by 1771 and the VCO frequency divided by 3997. As a result, the output of the frequency detector is at a low frequency, as corrections are made at these relatively small fractions of the VCO operating frequency. Thus the loop is slow to respond to changes in the control input (the reference input signal).
One proposed solution to this second problem is in the form of a variable rate pre-scaler, or a xe2x80x9cpulse swallowingxe2x80x9d pre-scaler. Such a device estimates reductions of fractions having large numerators and/or divisors to produce more manageable factors. Pulse swallowing pre-scalers are well known in the art and are able to mitigate the problem of large relatively prime M and N factors at the expense of added complexity. Nevertheless, there still exist problems of inaccuracy from the estimates made and slow speed from the calculations required to perform such reductions.
Another drawback to employing conventional phase locked loops is that the loop error is largely dependent on loop filter values. The values of resistance (xe2x80x9cRxe2x80x9d) and capacitance (xe2x80x9cCxe2x80x9d) in the loop filter can vary, and conventional loops, being second order control systems, are dependent on the relative value of at least two time constants. Finally, the design of a frequency control loop based on the measurement of phase in the loop error detector, whether or not pulse swallowing techniques are used, requires that the noise present at the error detector output is passed to the VCO control nodexe2x80x94this is a consequence of the required zero in the loop filter. Circuit designers have therefore been led to introduce yet a third frequency dependant component to xe2x80x9croll offxe2x80x9d this noise a pole frequency substantially above the loop unity gain cross over. Thus, at least two and possibly three or more frequency dependant elements must be designed in the conventional frequency control loop. All of these components necessarily have a bearing on the loop dynamics. As such, the components have an effect on the operation of the circuit loop, such as, settling time, stability, and other factors. Thus, choosing these values in a circuit is important to a circuit design and can be difficult.
Therefore, there exists a need for a device having improved performance factors over phase locked loops. As will be seen below, the invention accomplishes this in an elegant manner.
The invention provides a frequency locked loop and related method that enables the conversion of a signal frequency with improved stability. A frequency locked loop embodying the invention includes an input for receiving an input signal and an output for outputting an output signal having a different frequency than the input. A frequency detector is configured to receive the first factored input from the primary channel and the second factored input from the secondary channel, to calculate the difference between the first factored input and the second factored input and to produce an output based on the difference between the two factored inputs. A voltage controlled oscillator is configured to receive the output from the frequency detector, and to produce an output signal. The voltage controlled oscillator ultimately sets the output frequency based on the output of frequency detector. Unlike conventional frequency locked loops, the frequency detector receives the inputs from binary rate multipliers, which operate independently of whether the input factors require complex reduction; this is, independently of whether M and N are large and relatively prime the circuit is not burdened with slow correction, since the binary rate multipliers are not dependent on the reducibility of the respective input factors.
The invention provides a circuit configuration that operates faster and better that any conventional design and that has no inherent pole in the loop. Furthermore, a circuit configured according to the invention operates independent of whether M and N are relatively large irreducible numbers, such as prime numbers.